(1) Field of the Invention
The present invention relates to a high-speed polycrystalline silicon thin-film transistor (TFT) with three dimensional multichannel structure. More particularly, it relates to a high-speed TFT having three dimensional multichannel structure of which every side of a polycrystalline silicon film used as a semiconductive layer in a channel region is surrounded by a gate, and which is useful to ultra large scale integration (ULSI) circuits requiring a high-speed performance.
(2) Description of the Prior Art
Thin-film transistors (TFT's) have been used as switching devices for very large scale integrated circuits such as flat-panel liquid-crystal displays, image sensors, copying machines, printers, scanners, etc.
In accordance with the progress in the new display monitors such as high definition televisions (HDTV), etc., much study has been devoted to developing flat panel displays. Liquid crystal displays (LCD's) are representative of flat panel displays. They have desirable coloring, power consumption, and performance characteristics compared to electroluminescences (EL), vacuum fluorescence displays (VFD), plasma displays (PDP), etc. These LCD's generally include passive type and active type LCD's. In active type LCD's, each pixel is controlled by active devices such as TFT's, and are superior to passive type LCD's with respect to speed, viewing angle, and contrast ratio. Thus, they are the most suitable displays for HDTV, in which the reproduced image contains more than one million elements.
Conventional single crystalline silicon field effect transistors (FET) are difficult to manufacture for large scale displays and they cannot be formed on an insulating substrate such as glass. Their use tends to be limited to memory devices, commercial integrated circuits, etc. Polysilicon thin film transistors, however, have wide application for flat panel displays and image sensors that cannot be embodied with single crystalline silicon field effect transistors.
A polycrystalline silicon thin film transistor manufacturing technique, using a polycrystalline silicon film as a semiconductor within channel regions, is suitable for ultra-high-density large scale integrated circuits requiring high voltage and high current. The poly-Si TFT's, however, have unacceptably high leakage current compared to FET's made on the crystalline silicon substrate. This is because very thin semiconductive films, several hundred angsttoms thick, are deposited on an insulating substrate in the TFT's, and electrons induced to the channel regions are diffused throughout the Si substrate (like the FET's in an OFF state of the gate) and are reunited to be absorbed in drains.
There is another problem in that carrier mobility in the channel region is low, and the magnitude of the driving current, i.e., I.sub.ON, is small.
According to a conventional reverse staggered type TFT as shown in FIG. 1, a gate electrode 11 is formed on a substrate 10 made of an insulating material such as glass, and a gate insulating layer 12 is formed on the gate electrode 11. A semiconductive layer 13 is formed on the gate insulating layer 12 and ohmic contact layers 14 are formed on the right and left sides of the semiconductive layer 13, excluding a channel region. Finally, source/drain electrodes 15 are formed.
According to a conventional staggered type TFT as shown in FIG. 2, a gate electrode 25 is formed on a semiconductive layer 23, with a gate insulating layer 24 formed there between. Ohmic contact layers 22 are formed to the sides of the semiconductive layer 23 to be proximately aligned with the gate electrode 25. Source and drain electrodes 21 are formed on an insulating substrate 20.
The TFT having the conventional single gate electrode suffers from low channel conductance as well as the problems as mentioned above.
According to conventional technology, a double gate polycrystalline silicon metal oxide semiconductor FET (MOSFET) is proposed, having upper and lower gates and TFT with dual gate structure in which gates are formed side by side. The double gate structure is disclosed in pp. 393-396 of Extended Abstracts of 22nd Conference on SSDM, "Double-Gate Polysilicon MOSFET", published in 1990.
A side-sectional view of the double gate polycrystalline silicon MOSFET is shown in FIG. 3. The relation between gate voltage V.sub.c and transconductance g.sub.m according to gate structure is illustrated in FIG. 4.
As shown in FIG. 3, the MOSFET with double gate structure is formed as follows. A polycrystalline silicon film 33 is formed on a silicon substrate 30 on which an insulating layer 39 is deposited. Gate insulating layers 32 and 35 are interposed between a lower gate 31 and a upper gate 36. That is, each gate is formed on the lower and upper parts of a polycrystalline silicon film 33 used as a semiconductor channel region, such that the width of current passage from the source 34A to the drain 34B is twice as great as if only a single gate were used. A interlayer insulating layer 37 and a conductive layer for metallization 38 are also included. Accordingly, as depicted in FIG. 4, the transconductance g.sub.m, increases about twice as much compared with the conventional single gate MOSFET.
In the double gate FET, however, if the required area decreases so as to increase integrity, the channel region also decreases, and therefore the channel conductance decreases as well.
In order to obtain the characteristics as mentioned above, the thickness of the polycrystalline silicon film 33 between the double gates must be limited to about 100 angstroms, which is a significant barrier in ULSI's requiring high voltage and high current. The impossibility of applying high voltage thereto is a drawback to the LCD's aiming for integration with their peripheral circuits.
The mechanism of polysilicon thin film transistors having high voltage and high transconductance formed on a quartz substrate by a multiple strip polysilicon film is disclosed by Takashi Unagami under a title of "High-Voltage PolySi TFT's with Multichannel Structure" at pp. 2363 to 2367 of VOL. 35, IEEE TRANSACTIONS ON ELECTRON DEVICE, published on December, 1988.
In the TFT with multichannel structure in the above-described paper, a gate electrode is disposed on only a single side of the channel region for each strip. Since each strip has just one side-channel structure, there is a problem that channel conductance and current driving ability cannot be maximized.
The reduction of the channel length and channel width of the planar transistor is very important in the development of ULSI's. The reduction of the channel length, however, causes serious problems such as degradation in hot carrier-induction characteristics and decrease in the threshold voltage due to short channel effects. In addition, the reduction of the channel width brings about degradation in hot carrier-induction characteristics and current driving ability because of a strong electric field at the field isolation edges. These problems give rise to scaling limitations of planar transistors for future ULSI's.